Abstract—We report a fully integrated power amplifier (PA) in 45-nm CMOS SOI. Both stacking and parallel power combining are utilized to achieve 18.7 dBm peak output power. Each PA unit uses three cascaded gain stages with 2-stacked, 3-stacked, and 5-stacked architectures employed for the first, second, and third stages, respectively. The output powers of four PA units are combined by a low loss 4:1 zero-degree combiner. With 1.4W DC power consumption, the PA achieves 18.7dBm saturated output power and 4.8% power-added efficiency (PAE) at 200 GHz. The PA has a small-signal gain of 14.6 dB at 203.2 GHz with a 3-dB bandwidth of 9.4 GHz, and chip dimensions are 1.28mm×1.05 mm. To the author’s knowledge, this is the highest power and PAE achieved at 200GHz in silicon.
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