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Thumbnail for entry First Demonstration of Monolithic Silicon Photonic Integrated Circuit 32x32 Thin-CLOS AWGR for All-to-All Interconnections

00:58

First Demonstration of Monolithic Silicon…

First Demonstration of Monolithic Silicon Photonic Integrated Circuit 32x32 Thin-CLOS AWGR for All-to-All Interconnections

First Demonstration of Monolithic Silicon Photonic Integrated Circuit 32x32 Thin-CLOS AWGR for All-to-All Interconnections

Mingye Fu Abstract We designed, fabricated, and demonstrated the first monolithic silicon photonic Thin-CLOS AWGR. The fabricated Thin-CLOS has 32 ports and four 16-port silicon nitride AWGRs…

ecexpo 2022
3d
architecture
crosstalk
loss
interconnections
thing
power
scale
throughput
savings
goal
flux
posting
reconfigure
works
future
insertion
testing
chip
process
From  Philip Young 0 likes 23 plays 0  
Thumbnail for entry An FDD-based Full-Duplex Sub-THz Interconnect with Data-rate of 22.6 Gb/s and Energy-Efficiency of 1.58pJ/bit

05:07

An FDD-based Full-Duplex Sub-THz Interconnect…

An FDD-based Full-Duplex Sub-THz Interconnect with Data-rate of 22.6 Gb/s and Energy-Efficiency of 1.58pJ/bit

An FDD-based Full-Duplex Sub-THz Interconnect with Data-rate of 22.6 Gb/s and Energy-Efficiency of 1.58pJ/bit

Integrated Circuits and Systems 12 Team Lead: Xuan Ding Advisor: Prof. Gu

power
figure
bandwidth
efficiency
components
loss
transmitter
waveguide
points
error
care
paper
sensitivity
output
amplifier
path
measure
kilohertz
insertion
bands
From  Femi-Jide Akinmoladun 0 likes 23 plays 0