Background calibration of pipelined ADC - Yuanhao Shi

From Philip Young April 02, 2022

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Traditional designs of analog-to-digital converters use reference circuits that have very low output impedance to keep the reference voltage nearly constant even when it delivers signal-dependent current. Unfortunately, the resulting power dissipation in the reference circuit is usually a significant part of the overall power dissipation of the ADC.
To reduce the power dissipation, I’m going to talk about digital background calibration of reference errors in an example pipelined ADC.

Tags: ecexpo 2022

Appears In: ECExpo 2022

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Background calibration of pipelined ADC - Yuanhao Shi

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